This invention relates to a current-to-voltage interface circuit for translating the current output of a device to a logic level voltage for interfacing to a logic circuit.
In logic systems, it is often advantageous to use devices which produce outputs in the form of current, rather than voltage, signals. Transmission of current signals from one circuit to another can be accomplished with relatively small voltage levels. This reduces the potential for noise generation in the circuit due to capacitive coupling between connecting leads. This is especially important in chip-to-chip signal transmission where lead lengths are relatively long.
An example of such an application is the use of a high speed analog comparator, having current signal inputs and outputs, in an analog to digital converter (Harris Corp. part number HI574A). This comparator has an input current terminal, a reference current terminal, a strobe terminal, and first and second output current terminals. Under normal conditions, the strobe is inactive and the output stage of the comparator goes into a preferential state in which it sinks a constant current of approximately 500 microamps through the first current output, while no current flows in the second current output. When the strobe is activated, the comparator assumes one of two states: (1) if the input current is greater than the reference current, the output stage remains in the preferential state, with currents flowing in the first and second current output as stated above; (2) if the input current is less than the reference current, the output stage switches the current flows such that a constant current of approximately 500 microamps is sunk through the second current output, while no current flows in the first current output. When the strobe is active, the comparator inputs are disabled and the outputs remain in the state mandated by the condition of the inputs when the strobe was activated. When the strobe is inactive, the output stage of the comparator returns to the preferential state.
To utilize a comparator of this type in a digital logic circuit, it is necessary to translate, or convert, the described states of the current outputs to logic level voltage signals. The interface circuit must have current inputs, for connection to the current outputs of the comparator, and a logic level voltage output for interfacing to logic circuits. When the comparator is in the preferential state (i.e., current is flowing in the first current input), the interface circuit assumes a first logic level at the voltage output. If the comparator input current is greater than the reference current when the strobe is activated, the comparator remains in the preferential state and no logic level transition occurs at the interface circuit voltage output. Thus, the logic switching time delay for this condition is essentially zero. If the comparator input current is less than the reference current when the strobe is activated, a transition to a second logic level voltage will take place at the voltage output of the interface circuit in response to the switching of current flows in the current inputs. Thus, a particularly advantageous circuit for this application is one in which the logic switching time delay for the transition from the first logic level voltage to the second logic level voltage has been minimized. This can be achieved at the expense of a relatively slow second-to-first logic level transition (i.e., the circuit recovery time), since recovery to the preferential state takes place between clock pulses when the comparator/interface circuit combination is not being called upon to make a decision. As will be discussed in detail below, the interface circuit of the present invention has these advantageous features.
Accordingly, it is an object of the present invention to provide a circuit for interfacing comparators, and other devices having current signal outputs, with digital logic circuits.
Another object of the present invention is to provide an interface circuit of relatively simple design which can be implemented with a minimal number of devices in a relatively small area.
Still another object of the present invention is to provide an interface circuit wherein the switching delay for a transition from a first logic level output to a second logic level output is minimized.
A further object of the present invention is to provide a circuit with a high immunity from noise and erroneous signals when the output is in the first logic level state.
A still further object of the present invention is to provide a circuit wherein the first-to-second logic level voltage transition time and the second-to-first logic level voltage recovery time are easily adjusted by altering the relative sizes of circuit components.
These and other objects of the invention are attained by a current-to-voltage interface circuit which produces a first logic level voltage at a logic voltage output when current flows in a first current input, and which produces a second logic level voltage at the logic voltage output when current flows in a second current input. The interface circuit comprises an input stage and a logic stage. The input stage has first and second current inputs and a voltage output. The logic stage has an input connected to the voltage output of the input stage, and an output at which logic level voltages are produced. The input stage comprises a first circuit, a second circuit, and a switching device. The first circuit includes the first current input, a first current source and voltage clamping element, and a first voltage output connected to the switching device. The second circuit includes the second current input, a second current source and voltage clamping element, and a second voltage output connected at a node to the switching device and to the input of the logic stage. The switching device is connected to a voltage source and, in response to a voltage produced at the first voltage output by the first circuit, connects the voltage source to the logic stage input. Logic level voltage transitions are produced at the logic stage output in response to the voltage changes produced at the node where the logic circuit input, the second voltage output and the switching device are connected. The first-to-second and second-to-first logic level voltage transition times are adjustable by selecting first and second transistors in the first circuit such that, when both transistors are biased with the same voltage, the current established in the first transistor will be a selected multiple of the current established in the second transistor.